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CY28330
Clock Generator for AMDTM Hammer
Features
* Supports AMD Hammer CPU * 2 differential Pair of CPU Clocks * 6 Low Skew/Jitter PCI Clocks * 1 Free-running PCI Clock * 3 Low Skew/Jitter AGP/HT Clocks * 148M Output for USB * 1 programmable 24M or 48M for FDC * 3 REF 14.318MHz Clocks * Dial-a-Frequency Programmability * Cypress Spread Spectrum for Best EMI Reduction * SMBus Register Programmable Options * 5V Tolerance SCLK and SDATA Lines * 3.3V Operation * Power Management Control Pins * 48 Pin SSOP Package Table 1. Frequency Table (MHz)[1]
FS (3:0) CPU PCI_HT SEL PCI_HT PCI VC0 CPU PCI_H PCI Div T Div Div
0000 Hi-Z 0001 XIN 0001 XIN 0010 100.0 0011 100.0 0100 100.0 0101 133.3 0110 166.7 0111 200.0 1000 105.0 1001 110.0 1010 115.0 1011 120.0 1100 140.0 1101 150.0 1110 160.0 1111 180.0
=
X 0 1
Hi-Z XIN/3 XIN/6
Hi-Z XIN/6 XIN/6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3/6 3/6 3/6 4/8 5/10 6/12 3/6 3/6 3/6 4/8 4/8 5/10 5/10 6/12 6 6 6 8 10 12 6 6 6 8 8 10 10 12
0/1 66.7/33.3 33.31 200 0/1 66.7/33.3 33.31 200 0/1 66.7/33.3 33.31 200 0/1 66.7/33.3 33.31 266.6 0/1 66.7/33.3 33.31 333.3 0/1 66.7/33.3 33.31 400.0 0/1 70.0/35.0 35.00 210.0 0/1 73.3/36.7 36.67 220.0 0/1 76.7/38.3 38.33 230.0 0/1 60.0/30.0 30.00 240.0 0/1 70.0/35.0 35.00 280.0 0/1 60.0/30.0 30.00 300.0 0/1 64.0/32.0 32.00 320.0 0/1 60.0/30.0 30.00 360.0
Block Diagram
X IN XU OT 14.31818M z H XL TA /4 P LL1 24_48M H RF E (0:2)
Pin Configuration
FS0/REF0 VDD XIN XOUT VSS *PCI33HT66SEL# PCI33_HT66_0 PCI33_HT66_1 VDD VSS PCI33_HT66_2 *SRESET#/PD# PCI33_0 PCI33_1 VSS VDD PCI33_2 PCI33_3 VDD VSS PCI33_4 PCI33_5 FS3/PCI33_F PCISTOP# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Pull-up
UB S
/2 24_48M / H 24_48S L# E
FS (0:3) P IS P C TO # SRA PED C ontrol Logic SEE D R S T#/P # S LK C SA D TA
P LL2
CU P T(0:1) C U (0:1) PC
/N
P I33_F C
SP TO
P I33_(0:5) C
C TL N
P I33_H C T66_(0:2)
FS1/REF1 VSS VDD FS2/REF2 *SPREAD VDDA VSSA CPUT0 CPUC0 VSS VDD CPUT1 CPUC1 VDD VSS VSSF VDDF USB VSS VDD 24_48MHz/SEL# VSS SDATA SCLK
* = 150 K
Note: 1. All outputs except XOUT will be three-stated when FS(3:0) = 0000.
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
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CY28330
Pin Description
Pin 3 4 41, 37 40, 36 23 13, 14, 17, 18, 21, 22 7, 8, 11 Name XIN XOUT CPUT(0:1) CPUC(0:1) PCI33_F PCI33(0:5) PCI33_HT66(0:2) PWR VDD VDD VDDC VDDC VDD VDD VDD I/O I O O O O O O Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN. CPU clock outputs 0 and 1: push-pull "true" output of differential pair. CPU clock outputs 0 and 1: push-pull "compliment" output of differential pair. 3.3V free-running PCI clock output. 3.3V PCI clock outputs controlled by PCISTOP#. 3.3V PCI 33MHz or HyperTransport 66 clock outputs. This group is selectable between 33 MHz and 66 MHz based upon the state of the PCI33HT66SEL#. This input selects the output frequency of PCI33_HT66 outputs to either 33 MHz or 66 MHz. There is an internal 150K ohm pull-up resistor. This pin will be externally strapped low using a 10Kohm resistor to VSS. 0 = 66 MHz, 1 = 33 MHz. 3.3V USB clock output at 48 MHz. 3.3v Super I/O clock output. At power up this pin is sensed to determine whether the output is 24 MHz or 48 MHz. There is an internal 150K ohm pull-up resistor. This pin will be externally strapped low using a 10K ohm resistor to VSS. 0 = 48 MHz, 1 = 24 MHz. 3.3V Reference clock output. At power up this pin is sensed to determine the CPU output frequency. There is an internal 150K ohm pull-up resistor. These pins will be externally strapped low using a 10K ohm resistor to VSS. See Table 1. Spread Spectrum clock enable. At power up this pin is sensed to determine whether spread spectrum clocking in enabled on all output except the USB and 24_48/SEL#. There is an internal 150K ohm pull-up resistor. This pin will be externally strapped low using a 10K ohm resistor to VSS. 0=disable, 1=enable. Control for PCI33(0:5) and PCI33_HT66(0:2) outputs. Active LOW control input to halt all 33MHz PCI clocks except PCI33_F. Only the PCI33_HT66 outputs that are running at 33MHz will be stopped. The outputs will be glitch free when turning off and turning on. There is an internal 150K ohm pull-up resistor. SRESET output from Watchdog timer. Active low. Power-down input. 1 = running, 0 = Power Down. There is an internal 150K ohm pull-up resistor. Data pin for SMBus (rev2.0). Clock pin for SMBus (rev2.0). Power connection to 3.3V for the core. Power connection to GROUND for the CORE section of the chip.
6
PCI33_HT66SEL#
VDD
I PU
31 28
USB 24_48/SEL#
VDDF VDDF
O I/O PU
1, 48, 45
REF(0:2)/FS(0:2)
VDD
I/O PU
44
SPREAD
VDD
I PU
24
PCISTOP#
VDD
I PU
12
SRESET# PD#
VDD VDD VDD VDD
O I PU I/O I PWR GND
26 25 2, 9, 16, 19, 29, 35, 38, 46 5, 10, 15, 20, 27, 30, 34, 39, 47 43 42 32 33
SDATA SCLK VDD VSS
VDDA VSSA VDDF VSSF
PWR GND PWR GND
Power connection to 3.3V for the ANALOG section of the chip. Power connection to GROUND for the ANALOG section of the chip. Power connection to 3.3V for the 48-MHz PLL section of the chip. Power connection to GROUND for the 48-MHz PLL section of the chip.
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CY28330
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operation from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant Table 3. Block Read and Block Write protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Description Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 Bit '00000000' stands for block operation Acknowledge from slave Byte Count from master - 8 bits Acknowledge from slave Data byte 0 from master- 8 bits Acknowledge from slave Data byte 1 from master - 8 bits Acknowledge from slave Data bytes from master/Acknowledge Data Byte N - 8 bits Acknowledge from slave Stop Bit 1 2:8 9 10
Block Read Protocol Description Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 Bit '00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte 0 from slave - 8 bits Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop
11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... ....
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CY28330
Table 4. Byte Read and Byte Write protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Description Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Bit 1 2:8 9 10 11:18 Byte Read Protocol Description Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Serial Control Registers
Byte 0: Frequency and Spread Spectrum Control Register Bit 7 @Pup Inactive = 0 Description Write Disable (write once). A 1 written to this bit after a 1 has been written to Byte0 bit0 will permanently disable modification of all configuration registers until the part has been powered off. Once the clock generator has been Write Disabled, the SMBus controller should still accept and acknowledge subsequent write cycles but it should not modify any of the registers. Spread Spectrum enable (0=disable, 1=enable). This bit provides a SW programmable control for spread spectrum clocking. See Table 5. The readback version of this bit is the hardware strapped value such that the SW has the ability to know each state, either by readback or by writing the SSE bit. ATPG Mode. 0 = disable, 1 = enable. See Byte 8, bit 7. FS(3) (corresponds to Frequency Selection. See Table 1. FS(2) (corresponds to Frequency Selection. See Table 1. FS(1) (corresponds to Frequency Selection. See Table 1. FS(0) (corresponds to Frequency Selection. See Table 1. Write Enable. A 1 written to this bit after power up will enable modification of all configuration registers and subsequent 0's written to this bit will disable modification of all configuration except this single bit. Note that block write transactions to the interface will complete, however unless the interface has been previously un-locked, the writes will have no effect. The effect of writing this bit does not take effect until the subsequent block write command.
6
Inactive = 0
5 4 3 2 1 0
0 FS3 pin FS2 pin FS1 pin FS0 pin Inactive = 0
Table 5. Spread Spectrum Enable Pin 44 0 0 1 1 B0b6 0 1 0 1 Spread Enable Off On On On
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CY28330
Byte 1: PCI Clock Control Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 8 7 22 21 18 17 14 13 Name PCI33_HT66_1 PCI33_HT66_0 PCI33_5 PCI33_4 PCI33_3 PCI33_2 PCI33_1 PCI33_0 Test Condition enable (1=Enabled, 0=Disabled) enable (1=Enabled, 0=Disabled) enable (1=Enabled, 0=Disabled) enable (1=Enabled, 0=Disabled) enable (1=Enabled, 0=Disabled) enable (1=Enabled, 0=Disabled) enable (1=Enabled, 0=Disabled) enable (1=Enabled, 0=Disabled)
Byte 2: PCI Clock, USB, 24_48MHz, REF(0:2) Control Register Bit 7 6 5 4 3 2 1 0 @Pup active = 1 active = 1 active = 1 active = 1 active = 1 active = 1 active = 1 active = 1 Test Condition CPUT/C(1) shutdown. This bit can be optionally used to disable the CPUT/C(1) clock pair. During shutdown, CPUT=low and CPUC=high CPUT/C(0) shutdown. This bit can be optionally used to disable the CPUT/C(0) clock pair. During shutdown, CPUT=low and CPUC=high REF(2) enable (1=Enabled, 0=Disabled) REF(1) enable (1=Enabled, 0=Disabled) REF(0) enable (1=Enabled, 0=Disabled) 24_48MHz enable (1=Enabled, 0=Disabled) USB enable (1=Enabled, 0=Disabled) PCI33_HT66(2) enable (1=Enabled, 0=Disabled)
Byte 3: PCI Clock Free Running Select Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 Inactive = 0 Inactive = 0 Inactive = 0 Inactive = 0 Inactive = 0 Inactive = 0 Description PCI33 drive strength. 0 = normal, 1 = high. PCI33_HT66 drive strength. 0 = normal, 1 = high. PCI(5) free running enable (1=Free running, 0=Disabled) PCI(4) free running enable (1=Free running, 0=Disabled) PCI(3) free running enable (1=Free running, 0=Disabled) PCI(2) free running enable (1=Free running, 0=Disabled) PCI(1) free running enable (1=Free running, 0=Disabled) PCI(0) free running enable (1=Free running, 0=Disabled)
Byte 4: Pin Latched/Real Time State (and one free running control) Bit 7 6 5 4 3 2 1 0 @Pup active = 1 Pin 44 Pin 28 Pin 6 Pin 45 Pin 48 Pin 1 Pin 23 SPREAD pin state, not latched 24_48SEL# pin power up latched state PCI33_HT66SEL# pin statement latched FS(2) power up latched state FS(1) power up latched state FS(0) power up latched state FS(3) power up latched state Description PCI33_F output enable. This bit can be optional used to disable the PCI33_F output.
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CY28330
Byte 5: Clock Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 1 0 0 0 0 0 0 0 Vendor ID, Cypress = 100 Vendor ID Vendor ID Device Revision ID Device Revision ID Device Revision ID Device Revision ID Device Revision ID Description
Byte 6: SSCG, Dial-a-SkewTM and Dial-a-RatioTM Register Bit 7 6 5 4 3 2 1 @Pup 0 0 0 1 0 0 0 Description SS_MODE; 0 = down spread, 1 = center spread See Table 6. SST1 Select spread percentage. See Table 6. SST0 Select spread percentage. See Table 6. Reserved DASAG1; Programming these b its allow shifting the skew of the HT66(0:2) signals relative to their default value. See Table 7. DASAG0; Programming these bits allow shifting the skew of the HT66(0:2) signals relative to their default value. See Table 7. DARAG1; Programming these bits allow shifting the ratio of the HT66(0:2) signals relative to their default value. See Table 8. DARAG0; Programming these bits allow shifting the ratio of the HT(0:2) signals relative to their default value. See Table 8.
0
0
Table 6. Spread Spectrum Table SS_Mode (B6b7) 0 0 0 0 1 1 1 1 Table 7. Dial-a-Skew CPU to HT66 DASAG(1:0) 00 01 10 11 HT66 Skew Shift Default -150 ps + 150ps + 300 ps SST1 (B6b6) 0 0 1 1 0 0 1 1 SST0 (B6b5) 0 1 0 1 0 1 0 1 Table 8. Dial-a-Ratio CPU to HT66 DASAG(1:0) 00 01 10 11 CPU/HT66 Ratio Frequency selection default 2/1 2.5/1 3/1 % Spread -1.5% -1.0% -0.7% -0.5% 0.75% 0.5 0.35% 0.25%
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CY28330
Byte 7: Watchdog Control Register Bit 7 6 @Pup 0 0 Name Pin 12 Mode Select Frequency Reversion Description SRESET#; 1 = Pin 12 is the input pin which functions as a PD# signal. 0 = Pin 12 is the output pin as SRESET# signal. This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time out only. 0 = selects frequency of existing H/W setting 1 = selects frequency of the second to last S/W setting. (the software setting prior to the one that caused a system reboot). For Test, ALWAYS program to `0' WD Time-out WD3 WD2 WD1 WD0 This bit is set to "1" when the Watchdog times out. It is reset to "0" when the system clears the WD time stamps (WD3:0). This bit allows the selection of the time stamp for the Watchdog timer. See Table 9. This bit allows the selection of the time stamp for the Watchdog timer. See Table 9 This bit allows the selection of the time stamp for the Watchdog timer. See Table 9. This bit allows the selection of the time stamp for the Watchdog timer. See Table 9.
5 4 3 2 1 0
0 0 0 0 0 0
Table 9. Watchdog Time Stamp WD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Off 1 second 2 seconds 3 seconds 4 seconds 5 seconds 6 seconds 7 seconds 8 seconds 9 seconds 10 seconds 11 seconds 12 seconds 13 seconds 14 seconds 15 seconds
Byte 8: Dial-a-FrequencyTM Control Register N Bit 7 6 5 4 3 2 1 0 @PUp 0 N6 N5 N4 N3 N2 N1 N0 Description ATPG Pulse. A 0 to 1 transition on this bit will trigger a differential pulse on the CPUT/C lines whose pulse width is equal to the period of the currently latched frequency. These bits are for programming the PLL's internal N register. This access allows the user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU clock.
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CY28330
Byte 9: Dial-a-FrequencyTM Control Register M Bit 7 6 5 4 3 2 1 0 @Pup 0 R5 R4 R3 R2 R1 R0 0 When this bit = 1, it enables the Dial-a-Frequency N and R bits to be multiplexed into the internal N and R registers. When this bit = 0, the ROM based N and R values are loading into the internal N and R registers. Description CPU output skew; 0 = normal, 1 = -200ps Pin 41 to Pin 7 These bits are for programming the PLL's internal R register. This access allows the user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU clock.
ROM N Register
SMBus Byte8
Latch
Byte8 Write
R Register
SMBus Byte9
Byte9 Write
DAFEN
Figure 1. Dial-a-Frequency Register Loading
Dial-a-Frequency Feature
Dial-a-Frequency gives the designer direct access to the reference divider (M) and the feedback divider (N) of the internal Phase Lock Loop (PLL). The algorithm is the same for all P values, which is Fcpu = (P * N) / M with the following conditions. M = (20..56), N = (21..127) and N > M > N/2. `P' is a large value constant that translates the output of the PLL into the CPU frequency. The Value of `P' is relative to the latest frequency selected in the device prior to enabling the Dial-a-Frequency feature. Furthermore, P is an indication that the frequency ratios between the CPU, SDRAM, AGP (3V66), and PCI clock outputs remains unchanged when the Dial-a-Frequency feature is enabled. Table 10. FS(3:0) XXXX P 95995000
output may not occur immediately after this time as the PLL needs to be locked and will not output an invalid frequency. The CPU frequencies are defined from the hardware-sampled inputs. Additional frequencies and operating states can be selected through the SMBus programmable interface. Spread spectrum modulation is required for all outputs derived from the internal CPU PLL2 (see Block Diagram). This include the CPU(0:1), PCI33(0:5), PCI33_F and PCI33_HT66(0:2). The REF (0:2), USB and 24_48 clocks are not affected by the spread spectrum modulation. The spread spectrum modulation is set for both center and down modes using linear and Lexmark profiles for amounts of 0.5% and 1.0% at a 33KHz rate. The CPU clock driver is of a push-pull type for the differential outputs, instead of the AMD Athlon open-drain style. The CPU clock termination has been derived such that a 15-40 ohm, 3.3V output driver can be used for the CPU clock. The PCISTOP# signal provides for synchronous control over the any output, except the PCI33_F, that is running at 33MHz. If the PCI33_HT66 outputs are configured to run at 66MHz will not be stopped by this signal. The PCISTOP# signal is sampled by an internal PCI clock such that once it is sensed low or active, the 33MHz signals are stopped on the next high to low transition such that there is always a valid high signal.
Operation
Pin strapping on any configuration pin is based on a 10K ohm resistor connected to either 3.3V (VDD) or ground (VSS). When the VDD supply goes above 2.0V, the Power-On-Reset circuitry latches all of the configuration bits into their respective registers and then allows the outputs to be enabled. The
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CY28330
Absolute Maximum Rating
Parameter VDD, VDDA, VDDF VIN1, VIN2 TSTG ESDprotection Description Supply voltage Input voltage Storage temperature Input ESD (HBN) Rating -0.5 to 3.8 -0.5 to 3.8 -65 to +150 > 2,000 Unit V V C V
Operating Condition[2]
Parameter VDD, VDDA, VDDF TA Finput Supply voltage Operating temperature, Ambient Input frequency (crystal or reference) Description Min. 3.135 0 10 14.318 Typ. 3.3 Max. 3.465 70 16 Unit V C MHz
SCLK and SDATA Input Electrical Characteristics (5V tolerant)
Parameter VIL VIH IIL, IIH VOL IOL Description Supply voltage Input voltage Input high/low current Output high voltage Output low voltage 0DC Parameters (All outputs loaded)
Parameter VIL VIH IIL IIH Ioz Idd3.3V Ipd3.3V Cin Cout Lpin Cxtal VBIAS Txs Description Input Low Voltage Input High Voltage Input Low Current (@VIL = VSS) For internal Pull up resistors, See Note 4 Input High Current (@VIH =VDD) Three-State leakage Current Dynamic Supply Current Power Down Supply Current Input pin capacitance Output pin capacitance Pin inductance Crystal pin capacitance Crystal DC Bias Voltage Crystal Startup time From Stable 3.3V power supply. Measured from Pin to Ground. 27 0.3Vdd 36 Vdd/2 CPU(0:1) @ 200MHz 250 2 5 6 7 45 0.7Vdd 40 Conditions See Note 3 Min. VSS-0.3 2.0 Typ. Max. 0.8 VDD+0.3 -50 50 10 Unit V V A A A mA mA pF pF nH pF V s
Notes: 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Applicable to input signals: SPREAD, PCISTOP#, 24-48/Sel#. 4. Internal Pull-up and Pull-down resistors have a typical value of 250
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CY28330
AC Parameter
PCI133_HT66 = 66MHz Parameter TR TF VDIFF DVDIFF VCM VCM TD TJC TJA TJSC_OP TJSC_DC Description Output Rise Edge Rate Output Fall Edge Rate Differential Voltage Change in VDIFF_DC Magnitude Common Mode Voltage Change in VCM Duty Cycle Jitter, Cycle to Cycle Jitter, Accumulated Spectral Content Noise near Hammer frequency Spectral Content Noise from 0-200MHz Noise floor measured with Spread Spectrum on between 0 MHz and 200 MHz. Measured with a 3.3V PECL differential buffer in line with CPU clock output Measure from full supply voltage Average value during switching transition. Test Condition Measured @ the Hammer test load using VOCM400mV, 0.850V to 1.650V Measured @ the Hammer test load using VOCM 400mV, 1.650V to 0.850V Measured @ the Hammer test load (single ended) Measured @ the Hammer test load (single ended) Measured @ the Hammer test load (single ended) Measured @ the Hammer test load (single ended) Measured at VOX Measured at VOX Measured at VOX Min. 2 2 0.4 -150 1.05 -200 45 0 -1000 TBD TBD 50 100 1.25 1.25 Typ. Max. 7 7 2.3 150 1.45 200 53 200 1000 TBD TBD Unit V/ns V/ns V mV V mV % ps ps dB dB
TFS RON
Frequency Stabilization from Power-up Output Impedance
0 15 35
3 55
ms W
Table 11.PCI/Hyper Transport Clock Outputs PCI33, PCI33_HT = 33 MHz PCI33_HT = 66 MHz Parameter VOL VOH IOL IOH F TR TF TD TJC TJA TFS RON Description Output Low Voltage Output High Voltage Output Low Current Output High Current Frequency Actual Output Rise Edge Rate Measured from 20% to 60% Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Jitter Accumulated Measured from 60% to 20% Measured at 1.5V Measured at 1.5V Measured at 1.5V 1 1 45 0 -1000 0 12 15 Conditions IOL = 9.0mA IOH =-12.0mA VO = 0.8V VO = 2.0V 33.33 4 4 55 250 1000 3 55 12 15 1 1 45 0 -1000 Min. 2.4 10 -15 66.67 4 4 55 250 1000 3 55 Typ. Max. 0.4 2.4 10 Min. Typ. Max. 0.4 -15 Unit V V mA mA MHz V/ns V/ns % ps ps ms W
Frequency Stabilization Measure from full supply from Power-up voltage Output Impedance Average value during switching transition.
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CY28330
Table 12.REF(0:2) Clock Outputs PCI133_HT66 = 66 MHz Parameter VOL VOH IOL IOH F TR TF TD TJC TJA TFS RON Description Output Low Voltage Output High Voltage Output Low Current Output High Current Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Jitter, Accumulated Output Impedance Measured from 20% to 60% Measured from 60% to 20% Measured at 1.5V Measured at 1.5V Measured at 1.5V Average value during switching transition. 0.5 0.5 45 0 -1000 0 20 24 500 Test Condition IOL = 9.0 mA IOH = -12.0 mA VO = 0.8V VO = 2.0V 14.318 2 2 55 1000 1000 3 60 2.4 16 -22 Min. Typ. Max. 0.4 Unit V V mA mA MHz V/ns V/ns % ps ps mS W
Frequency Stabilization from Power-up Measure from full supply voltage
Table 13.USB, 24_24 Clock Outputs PCI33, PCI33_HT = 33MHz Parameter VOL VOH IOL IOH F TR TF TD TJC TJC TJA TFS RON Description Output Low Voltage Output High Voltage Output Low Current Output High Current Frequency Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Measured from 20% to 80% Measured from 80% to 20% Measured at 1.5V 0.5 0.5 45 0 250 Conditions IOL = 9.0mA IOH =-12.0mA VO = 0.8V VO = 2.0V 24.004 2 2 55 500 0.5 0.5 45 0 0 -1000 0 20 24 1000 3 60 -1000 0 20 24 250 2.4 16 -22 48.008 2 2 55 500 100 1000 3 60 Min. Typ. Max. 0.4 2.4 16 -22 PCI33_HT = 66MHz Min. Typ. Max. 0.4 Unit V V mA mA MHz V/ns V/ns % ps ps ps ms W
Jitter, Cycle-to-Cycle 24_48 Measured at 1.5V MHz Jitter, Cycle-to-Cycle USB Jitter Accumulated Measured at 1.5V Measured at 1.5V
Frequency Stabilization from Measure from full supply Power-up voltage Output Impedance Average value during switching transition.
Table 14.Skew [5] Parameter TSK_CPU_CPU TSK_CPU_PCI33 Description CPU to CPU skew, time independent Conditions Measured @ crossing points for CPUT rising edges1 Skew Window Unit 250 500 500 ps ps ps
CPU to PCI33 skew, time Measured @ crossing points for CPUT rising edge and independent 1.5V PCI clocks Measured between rising @ 1.5V
TSK_PCI33_PCI33 PCI33 to PCI33 skew, time independent
Note: 5. All skews in this skew budget are measured from the first referenced signal to the next. Therefore, this skew specifies the maximum SKEW WINDOW between these two signals to be 500ps whether the CPU crossing leads or lags the PCI clock. This should NOT be interpreted to mean that the PCI33 edge could either be 500ps before the CPU clock to 500ps after the clock, thus defining a 1000ps window in which the PCI33 clock edge could fall.
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Table 14.Skew (continued)[5] Parameter Description Conditions Skew Window Unit 500 500 500 200 200 200 200 200 200 ps ps ps ps ps ps ps ps ps TSK_PCI33_HT66 PCI33 to HT66 skew, time Measured between rising @ 1.5V independent TSK_CPU_HT66 CPU to HT66 skew, time independent Measured @ crossing points for CPUT rising edge and 1.5V for HyperTransport clocks
TSK_HT66_HT66 HT66 to HT66 skew, time Measured between rising @ 1.5V independent TSK_CPU_CPU CPU to CPU skew, time variant Measured @ crossing points for CPUT rising edges
TSK_CPU_PCI33 CPU to PCI33 skew, time Measured @ crossing points for CPUT rising edge and variant 1.5V PCI clocks TSK_PCI33_PCI33 PCI33 to PCI33 skew, time variant Measured between rising @ 1.5V
TSK_PCI33_HT66 PCI33 to HT66 skew, time Measured between rising @ 1.5V variant TSK_CPU_HT66 CPU to HT66 skew, time variant Measured @ crossing points for CPUT rising edge and 1.5V for HyperTransport clocks
TSK_HT66_HT66 HT66 to HT66 skew, time Measured between rising @ 1.5V variant Table 15.Loading Table Clock Name CPU(0:1) USB 24_48, REF (0:2) PC133(0:5), PC133_F, PCI33_HT66(0:2)
Max Load (in pF)[6] See Figure 2 20 30
Vbias=1.25V 125 ohms 15 ohms 3900pF 169 ohms 15 ohms 3900pF 5pF 5pF 125 ohms
Figure 2. Test Load Configuration
Note: 6. The above loads are positioned near each output pin when tested.
Rev 1.0, November 21, 2006
Page 12 of 14
CY28330
SRESET#/PD# CPUT(0:1) CPUC(0:1) PCI/PCI_HT USB,24_48MHz REF(0:2)
Figure 3. PD# Assertion Waveform
PD# CPUT CPUC PCI 33MHz
3V66 USB 48MHz REF 14.318MHz
Figure 4. PD# Deassertion Waveform
Rev 1.0, November 21, 2006
Page 13 of 14
CY28330
Ordering Information
Part Number Package Type Product Flow
CY28330OC CY28330OCT
48-pin SSOP 48-pin SSOP-Tape and Reel
Commercial, 0 to 70 C Commercial, 0 to 70 C
Package Drawing and Dimensions
48-pin Shrunk Small Outline Package O48
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 21, 2006
Page 14 of 14

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